.ALIASES
V_charge_ref          charge_ref(+=N61117 -=0 ) CN @NON_DIFF_SIM.SCHEMATIC1(sch_1):INS69174@SOURCE.VDC.Normal(chips)
V_V2            V2(+=N68433 -=0 ) CN @NON_DIFF_SIM.SCHEMATIC1(sch_1):INS68225@SOURCE.VDC.Normal(chips)
X_U1C           U1C(+=N61117 -=N61101 V+=N68433 V-=0 OUT=N74717 ) CN
+@NON_DIFF_SIM.SCHEMATIC1(sch_1):INS74252@OPAMP.LM324.Normal(chips)
X_U1A           U1A(+=N65310 -=N65599 V+=N68433 V-=0 OUT=N65500 ) CN
+@NON_DIFF_SIM.SCHEMATIC1(sch_1):INS74042@OPAMP.LM324.Normal(chips)
R_R7            R7(1=N65310 2=N65908 ) CN @NON_DIFF_SIM.SCHEMATIC1(sch_1):INS64894@DISCRETE.R.Normal(chips)
V_load_vef          load_vef(+=N69834 -=0 ) CN @NON_DIFF_SIM.SCHEMATIC1(sch_1):INS69256@SOURCE.VDC.Normal(chips)
R_R4            R4(1=N61101 2=0 ) CN @NON_DIFF_SIM.SCHEMATIC1(sch_1):INS61063@DISCRETE.R.Normal(chips)
V_V5            V5(+=N59430 -=N65908 ) CN @NON_DIFF_SIM.SCHEMATIC1(sch_1):INS70464@SOURCE.VDC.Normal(chips)
V_V1            V1(+=N59430 -=0 ) CN @NON_DIFF_SIM.SCHEMATIC1(sch_1):INS59142@SOURCE.VDC.Normal(chips)
R_10k           10k(1=N65310 2=N69834 ) CN @NON_DIFF_SIM.SCHEMATIC1(sch_1):INS64974@DISCRETE.R.Normal(chips)
R_R3            R3(1=N59694 2=N65908 ) CN @NON_DIFF_SIM.SCHEMATIC1(sch_1):INS59432@DISCRETE.R.Normal(chips)
R_R5            R5(1=N65599 2=N65500 ) CN @NON_DIFF_SIM.SCHEMATIC1(sch_1):INS64734@DISCRETE.R.Normal(chips)
R_R8            R8(1=N59430 2=N65908 ) CN @NON_DIFF_SIM.SCHEMATIC1(sch_1):INS70768@DISCRETE.R.Normal(chips)
X_U1B           U1B(+=N65500 -=N59694 V+=N68433 V-=N65908 OUT=N59766 ) CN
+@NON_DIFF_SIM.SCHEMATIC1(sch_1):INS74147@OPAMP.LM324.Normal(chips)
R_R6            R6(1=0 2=N65599 ) CN @NON_DIFF_SIM.SCHEMATIC1(sch_1):INS64814@DISCRETE.R.Normal(chips)
_    _(GND_0=0)
.ENDALIASES
